Why 1.6T Networking Is Rapidly Becoming the Cornerstone of Next-Generation AI Clusters

For years, discussions about AI infrastructure have fixated on compute density: teraflops, GPU generations, and the raw number of accelerator cores packed into a single server. However, as clusters expand into the hundreds of thousands of XPUs, a different reality has emerged. The network is no longer just a passive transport layer. Today, it sits squarely on the critical path of large-scale AI training and inference workloads, meaning cluster-wide performance hinges as much on fabric design as on the chips themselves.

From Bottleneck to Strategic Asset

Synchronous collective communication—the foundational pattern of distributed AI training—involves tightly coordinated data exchanges among massive groups of GPUs. During this process, just one stalled flow can idle thousands of accelerators, waiting for the slowest participant to catch up. This dynamic creates a performance profile that traditional Ethernet, optimized for bursty web traffic and best-effort delivery, was never built to handle.

The scale of the problem is staggering. A recent survey found that 39% of organizations lose 30% to 50% of AI performance solely to networking limitations, while gradient exchanges consume an average of 62% of total execution time in production workloads. Worse, even 0.1% packet loss can slash GPU utilization by 13%, and at 1% loss, GPUs may spend less than five percent of their time actually computing. As AI workloads continue to explode, the industry is realizing that network architecture has become the defining constraint—and the most urgent strategic priority.

The 1.6T Switching Revolution

The answer to this bottleneck lies in a new generation of switching silicon designed specifically for AI. Enter the 102.4 Tbps switch ASIC, a class of devices that doubles the bandwidth of the previous generation and introduces dedicated AI-centric features. Leading this charge is Broadcom’s Tomahawk 6, which began shipping in production volume with both standard and co-packaged optics variants.

The numbers are telling. Tomahawk 6’s 102.4 Tbps of aggregate bandwidth is enough to support up to 512 ports at 200 Gbps or, for maximum port speed, 64 ports at 1.6 Tbps. It achieves this through 200Gbps PAM4 SerDes, with flexible configurations of either 1,024 100G lanes or 512 200G lanes. Crucially, the chip supports both RoCE and the emerging Ultra Ethernet standard, making it suitable for a broad range of AI fabrics. Perhaps most significantly for cluster architects, Tomahawk 6 can support scale-out networks of up to 128,000 GPUs using just two tiers of switching—where three tiers would have been required previously. This flatter topology reduces latency by minimizing hops, simplifies congestion control, and roughly halves the power and optics count required for equivalent performance.

Optics at the Core: Transceivers Keep Pace

Switching silicon alone does not solve the problem. For 1.6T networking to move from specifications to deployment floors, optical transceivers must deliver the required reach, power efficiency, and density. This is where a range of established and emerging modules come into play. For shorter links within a rack or across adjacent racks, reliable modules like the QSFP-40/100-SRBD continue to play a practical role in many existing cluster interconnects, providing a cost-effective bridge within certain segments of the physical cabling plant. Meanwhile, at the higher-density aggregation layers, the 100G QSFP28 remains a ubiquitous building block for assembling 100G fabric links in legacy and hybrid clusters.

Looking ahead, 1.6T transceivers are undergoing a rapid transition from pilot programs to mainstream deployment. Industry estimates place global 1.6T demand at approximately 500,000 to one million units in 2025, rising to roughly five million units in 2026 as hyperscalers accelerate their infrastructure investments. The IEEE 802.3dj Working Group is expected to finalize the 1.6TbE Ethernet standard in 2026, while the Ethernet Alliance’s 2026 roadmap already extends beyond 1.6T to 3.2T and higher speeds, driven entirely by AI workloads. At OFC 2026, the technology dominated the show floor, with virtually every major optical vendor demonstrating 1.6T modules based on silicon photonics, 3nm DSPs, and advanced packaging. Silicon photonics has emerged as the mainstream approach, with over 80% penetration in the 1.6T segment, while linear pluggable optics (LPO) offer up to 50% power reductions compared to traditional retimed modules.

A Unified Fabric for the AI Era

Perhaps the most transformative trend is not the speeds themselves, but the move toward a converged, open networking fabric. Historically, InfiniBand dominated AI training clusters, but Ethernet’s total addressable market in data center scale-up is projected to exceed $250 billion as hyperscalers standardize on open Ethernet fabrics for both training and inference. Initiatives like the Ultra Ethernet Consortium and UALink are driving interoperability, ensuring that 1.6T networking can become the unified backbone for the next generation of AI clusters.

For infrastructure teams planning their 2026–2027 roadmaps, the message is clear. The era of treating the network as an afterthought to compute is over. With 1.6T switching, 200G SerDes, and commercial optical modules all converging, the industry finally has the tools to build AI clusters where the fabric is no longer the weakest link—but the strongest foundation of all.